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Task 1. Time characteristics of a PCM trunk

1×n×r digital trunk conveys information. Quantity of time channels (TC) (n) per cycle and digit capacity of every time channel (r) are given in the table below.

Table 1 – Task variants 1 Calculate time characteristics (cycle duration, time channel duration, digit duration) and information bit rate of the trunk if sampling frequency fS = 8 kHz.

2 Draw a time chart of the calculated trunk. Mark all the parameters at the time chart.

3 Methodical instructions

Value of sampling frequency is given, which means we can easily calculate cycle’s period (duration) T = 1/fS = 1/8000 = 125 mkS. Every cycle consists of time channels. Duration of a time channel tn = T/n. Every time channel carries definite quantity of bits. Therefore duration of every bit tb = tn/r. Frequency of code elements (bits) fe = fs ×n×r coincides with bit rate V = fe. Figure 1 – Time chart of information transmission

The time chart must depict two cycles. It is necessary to mark 0, 1, and n-1 time channels of every cycle. Show all the bits of time channel number 1. The diagram should contain all the calculated values.

Task 2. Synthesis of space switching unit

A digital switching network is built upon N×n×r space switching unit (SSU). The SSU connects ILj to OLk during TCi. Quantity of time channels (TC) (n) and digit capacity of every time channel (r) are given in the table 1. Quantity of trunks (N), switching data (ILj, OLk, TCi) and chips’s type can be found in the table 2.

Table 2 – Task variants NOTE. Numeration of lines, TCs, and bits ranges from 0 to (n – 1) or (r – 1).

1 Calculate quantity of multiplexers (or demultiplexers) required for the N×n×r SSU. Calculate parameters of multiplexers (or demultiplexers).

2 Complete table of binary addresses for MXs (or DMXs) operation.

3 Calculate the following parameters of control memory.

– Quantity of required CM sections.

– Quantity of memory cells for every CM section.

– Digit capacity of every cell.

4 Draw a bloc diagram of your SSU. The diagram must contain multiplexers (or demultiplexers) performing given switching.

5 Determine switching data to write to an appropriate memory cell of control memory.

6 Briefly describe the process of switching (connection of ILj, OLk within TCi).

3 Methodical instructions

1 Quantity of required MXs or DMXs equals the quantity of supported trunks. A multiplexer is shown in the figure 2. Every multiplexer has information inputs (X0, X1,…) according to the quantity of supported trunks. Switching data comes to address inputs (A, B,…) of the multiplexer. Commutation bit comes to the multiplexer’s E input. Every multiplexer supports only one output (Q). Commutation bit coming to the multiplexer makes it select one of the information inputs according to binary address at the address inputs of the multiplexer. Thus, the selected input is connected to the output. Figure 2 – Multiplexer supporting 4 inputs

A demiltiplexer is a device having one input and many outputs.

If a space switching unit is built upon MXs then input lines must be connected to the address inputs of the multiplexers. Moreover, every input line must be connected to every multiplexer whilst output line is connected to an output of a multiplexer.

If a space switching unit is built upon DMXs then input line is connected to the single input of a DMX while output lines are connected to the outputs of the DMX. Moreover, all the output lines must be connected to all the DMXs. Figure 3 – Space switching units

2 One section of control memory controls one MX or DMX. Quantity of required MXs or DMXs equals the quantity of supported trunks (N). Every section of control memory contains n memory cells. n = quantity of time channels within a digital line (ncells of CM = nTC). Digit capacity of a cell r = 1+ log2(N).

3 Drawing the diagram of SSU make sure that:

– Executive part of your SSU contains 0, 1-st and the last MX (DMX) as well as the multiplexer (or demultiplexer) required to perform the given switching.

– The given IL, OL and TC are marked with another color.

– Control part of the SSU contains the sections of control memory (one section for each MX or DMX) for drawn MXs or DMXs. Every 0, 1-st and the last memory cell is shown at every section. Moreover, the memory cell involved in switching must be shown as well as its binary content.

4 Figure 3 shows MX and DMX space switching units.

Task 3. Synthesis of time switching unit

A digital switching network is built upon 1×n×r time switching unit (TSU). The time switching unit transfers information from TCi to TCj within one line.

Use the table 1 to obtain the quantity of time channels (n) and digit capacity of every time channel (r). Switching data (TCi and TCj) and mode of TSU operation can be obtained from the table 3.

Table 3 – Task variants NOTE. Mode 1 Writing of the code words from the input line to the IM is performed with the random access to the cells according to the addresses obtained from CM. In this mode the code words are read out to the output lines with the sequential access to the cells.

Mode 2 Writing of the code words from the input line to the IM is performed with the sequential access to the cells. And the code words are read out to the output lines with the random access to the cells according to the addresses obtained from CM.

1 Determine quantity of necessary memory cells for information memory (IM) and control memory (CM) of the TSU. Determine digit capacity of IM and CM cells.

2 Draw a bloc diagram of your TSU. The diagram must depict some IM and CM cells including the cells involved in switching.

3 Determine content of memory cells involved in switching.

4 Shortly describe switching process.

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